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Date Session Title Start Time End Time
2014-01-28

Hands-On Tutorial for Fixture Removal of 28Gbps Tx Measurements

Date: 2014-01-28
Time: 09:00:00-05:00 - 12:00:00-05:00


General Session Files:
09:00:00-05:00 12:00:00-05:00
2014-01-28

High Density High Performance Package and 2.5D/3D Interconnect Design

Date: 2014-01-28
Time: 09:00:00-05:00 - 12:00:00-05:00


Speaker - Joungho Kim, Professor, TERA Laboratory at KAIST

Speaker - Madhavan Swaminathan, Professor, Georgia Institute of Technology

Speaker - John Xie, Director of Packaging Technology R&D, Altera Corporation

Speaker - Paul Franzon, Professor, North Carolina State University

Speaker - Zhe Li, Package R&D Engineer, Altera Corporation
09:00:00-05:00 12:00:00-05:00
2014-01-28

An Implementer's Guide to Low-Power and High-Performance Memory Solutions

Date: 2014-01-28
Time: 09:00:00-05:00 - 12:00:00-05:00


General Session Files:
09:00:00-05:00 12:00:00-05:00
2014-01-28

Design and Verification for High-Speed I/Os at Multiple to 56 Gbps with Jitter, Signal Integrity, and Power Optimization

Date: 2014-01-28
Time: 09:00:00-05:00 - 12:00:00-05:00


General Session Files:
09:00:00-05:00 12:00:00-05:00
2014-01-28

Differential Signal Routing for PCB Designers

Date: 2014-01-28
Time: 09:00:00-05:00 - 12:00:00-05:00


General Session Files:
09:00:00-05:00 12:00:00-05:00
2014-01-28

Keynote Address & Best Paper Awards

Date: 2014-01-28
Time: 12:00:00-05:00 - 12:45:00-05:00


Speaker - Dr. Hermann Eul, VP & General Manager, Intel Corporation
12:00:00-05:00 12:45:00-05:00
2014-01-28

System Level Modeling Methodologies for PCB-Package Co-Simulation & Co-Design

Date: 2014-01-28
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
13:30:00-05:00 16:30:00-05:00
2014-01-28

Tips on Improving Test Time When Measuring High-Speed Digital Signals

Date: 2014-01-28
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
13:30:00-05:00 16:30:00-05:00
2014-01-28

Relating COM to Familiar S-Parameter Parametric to Assist 25Gbps System Design

Date: 2014-01-28
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
13:30:00-05:00 16:30:00-05:00
2014-01-28

Practical Measurements of Dielectric and Loss of PCB Materials at High Frequencies

Date: 2014-01-28
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
13:30:00-05:00 16:30:00-05:00
2014-01-28

Accurate Modeling of Electronic Package Designs: Hybrid vs. 3D EM Full Wave Solvers

Date: 2014-01-28
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
13:30:00-05:00 16:30:00-05:00
2014-01-28

Modeling Phase-Locked Loops for AMS Design and Verification

Date: 2014-01-28
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
13:30:00-05:00 16:30:00-05:00
2014-01-28

Essential Principles of Jitter

Date: 2014-01-28
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
13:30:00-05:00 16:30:00-05:00
2014-01-28

Battle on the Chip: Embed vs. De-Embed? - Panel Discussion

Date: 2014-01-28
Time: 16:45:00-05:00 - 18:00:00-05:00


General Session Files:
16:45:00-05:00 18:00:00-05:00
2014-01-29

Sources and Compensation of Skew in Single-Ended and Differential Interconnects

Date: 2014-01-29
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2014-01-29

SoC Power Integrity from Early Estimation to Design Signoff

Date: 2014-01-29
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2014-01-29

10.3Gbps Link Optimization and Its Impact on Jitter

Date: 2014-01-29
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2014-01-29

Worst Case Eye Estimation Method Considering Power Noise on Tx Output Driver and Channel Crosstalk & ISI in Interposer-Based 2.5D Interfaces

Date: 2014-01-29
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2014-01-29

Lessons learned: How to Make Predictable PCB Interconnects for Data Rates of 50 Gbps and Beyond

Date: 2014-01-29
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-29

SESSION CANCELED: Power Management Network Design Methodology and Verification to Secure RFID Product Tape-Out

Date: 2014-01-29
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-29

Improving Crosstalk and Voltage Noise Immunity of On-Chip High Speed Source-Synchronous Busses

Date: 2014-01-29
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-29

Converting Verilog/System Verilog to C++ for Usage with Data Flow Simulators and IBIS-AMI

Date: 2014-01-29
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:

Speaker - Todd Bermensolo, Signal Integrity Engineer, Intel Corporation
09:20:00-05:00 10:00:00-05:00
2014-01-29

Model Based Precise Link Budget Analysis of an Ad Hoc Serial Channel Considering Signal Path and PDN Interactions

Date: 2014-01-29
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-29

The Jitter-Noise Duality and Anatomy of an Eye-Diagram

Date: 2014-01-29
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-29

Versatile IO Circuit Schemes for LPDDR4 with 1.8mW/Gbps/pin Power Efficiency

Date: 2014-01-29
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-29

A Loewner-Matrix-Based Algorithm for State-Space Fitting of Frequency-Domain Data with Nonuniform Frequency Sampling

Date: 2014-01-29
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-29

100G Margins: BER Performance, Correlation to Measurements, and Improvement Opportunities

Date: 2014-01-29
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-29

Practical Design Considerations for Dense, High-Speed, Differential Stripline PCB Routing Related to Bends, Meanders and Jog-outs

Date: 2014-01-29
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-29

Optimizing On Die Decap in a System at Early Stage of Design Cycle

Date: 2014-01-29
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-29

Analysis and Correlations of Supply Noise and Jitter Impact on DDR3L Memory Interface

Date: 2014-01-29
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-29

Top Down design Methodology for Enhanced Electromagnetic Band Gap Structures

Date: 2014-01-29
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-29

Optimizing DDR4 PHY Design to Reduce the System-Level Jitter Impact by Supply Noise

Date: 2014-01-29
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-29

Practical Method for Measuring Digital Driver Impedance

Date: 2014-01-29
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-29

Package-PCB Interface Discontinuity Optimization for 50Gb/s Serdes Applications

Date: 2014-01-29
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-29

Modeling and Mitigating Power Supply Noise in Quad-Core CPU SoC & GPU Chipsets

Date: 2014-01-29
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-29

Mechanism of Jitter Amplification in Clock Channels

Date: 2014-01-29
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-29

Computation of Time Domain Impedance Profile from S-Parameters: Challenges and Methods

Date: 2014-01-29
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-29

Keynote Address & DesignVision Awards

Date: 2014-01-29
Time: 12:00:00-05:00 - 12:45:00-05:00


Speaker - Eileen Bartholomew, Sr. VP, Prize Development, XPRIZE Foundation
12:00:00-05:00 12:45:00-05:00
2014-01-29

Methodologies for Stressed Receiver Testing of 100Gb/sec Serial Communications Systems

Date: 2014-01-29
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-29

Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of DDR4 Memory Interface Applications.

Date: 2014-01-29
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-29

Distributed Modeling and Characterization of On-Chip/System Level PDN and Jitter Impact

Date: 2014-01-29
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-29

Have Your Cake and Eat It, Too: Engineering Measurements at Fabrication for Channel Design and Process Control

Date: 2014-01-29
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-29

Practical Techniques and Tips for Probing and De-Embedding

Date: 2014-01-29
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-29

IBIS AMI Modeling of Retimer and Performance Analysis of Retimer Based Active Serial Links

Date: 2014-01-29
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-29

Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies

Date: 2014-01-29
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-29

Analyzing Impact of On-Chip Supply Noise Induced Jitter

Date: 2014-01-29
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-29

The Road to 1TBps Bandwidth Systems: A Case Study

Date: 2014-01-29
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-29

Circuit Board Material Properties Considerations for Designing Advanced High Speed / High Frequency Multilayer Circuit Boards

Date: 2014-01-29
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-29

Strengths and Weaknesses of Various Calibration Techniques

Date: 2014-01-29
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-29

Powering the Next Mobile Generation: An Industry Overview of UFS - Panel Discussion

Date: 2014-01-29
Time: 15:45:00-05:00 - 17:00:00-05:00


General Session Files:
15:45:00-05:00 17:00:00-05:00
2014-01-29

System-Level Power Integrity: Tools Providers and Tool Users Engage - Panel Discussion

Date: 2014-01-29
Time: 15:45:00-05:00 - 17:00:00-05:00


General Session Files:
15:45:00-05:00 17:00:00-05:00
2014-01-29

How PCB Design is Changing: Simulation and Design Techniques - Panel Discussion

Date: 2014-01-29
Time: 15:45:00-05:00 - 17:00:00-05:00


General Session Files:
15:45:00-05:00 17:00:00-05:00
2014-01-30

High-Speed Link Simulation Strategy for Meeting Ultra Long Data Pattern Under Low BER Requirements

Date: 2014-01-30
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2014-01-30

Elimination of Conductor Foil Roughness Effects in Characterization of Dielectric Properties of Printed Circuit Boards

Date: 2014-01-30
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2014-01-30

Improved Statistical Link Path Analysis Considering Both Channel ISI and Supply Voltage Fluctuations

Date: 2014-01-30
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2014-01-30

New Methodology for 25+ Gbps Connector Characterization

Date: 2014-01-30
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-30

Modeling, Extraction and Verification of VCSEL Model for Optical IBIS AMI

Date: 2014-01-30
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-30

Method for Analytically Calculating BER (Bit Error Rate) in Presence of Non-Linearity

Date: 2014-01-30
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-30

Partial Response Maximum Likelihood Equalization and Detection for DSP Based Serdes With Cross Talk and Practical Equalization

Date: 2014-01-30
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-30

Real-Time Jitter Measurement

Date: 2014-01-30
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-30

Troubleshooting Radiated Emissions Using Your Own Low-Cost Troubleshooting Kit

Date: 2014-01-30
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-30

Power Integrity Analysis of Chip-Package-System (CPS) of a Mobile AP Using Extended CPM Technique

Date: 2014-01-30
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2014-01-30

Low Jitter S-Band Oscillators and VCOs in a Small CSP Suitable for Integration into ASICs

Date: 2014-01-30
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:

Speaker - Rich Ruby, Director of Technology, Avago Technologies, Ltd.
10:15:00-05:00 10:55:00-05:00
2014-01-30

111.18 Gbit/s G-FEC Design for OTN Application: Theory and Implementation Techniques

Date: 2014-01-30
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-30

Quantitative EMI Analysis of Electrical connectors Using Simulation Models

Date: 2014-01-30
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-30

Overcoming the SI Challenges in Designing 25-40 Gb/s Backplane Channels

Date: 2014-01-30
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-30

Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems

Date: 2014-01-30
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-30

Correlation of measurement and simulation results using IBIS-AMI models on measurement instruments

Date: 2014-01-30
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-30

Effective Conductivity Concept for Modeling Conductor Surface Roughness

Date: 2014-01-30
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2014-01-30

High Speed Serial Link Simulation Based on Dynamic Modeling

Date: 2014-01-30
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-30

Reducing Signal Transmission Loss by Low Surface Roughness

Date: 2014-01-30
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-30

Efficient Circuit-Level Implementation of Knuth-Based Balanced and Nearly-Balanced Codes for High Speed Parallel Bus Zero Sum Signaling

Date: 2014-01-30
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-30

On-Chip Aware Package and Board Integrated Simulation on Conducted Emission Noise Estimation for Avoiding Radio Frequency Interference

Date: 2014-01-30
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-30

Mixed-Reference for Optimum Cost & Performance in High-Speed Memory Interface

Date: 2014-01-30
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-30

Measured Random Jitter in a 300 GBit Optical Data Link Using a Chip-Scale FBAR Oscillator for the Reference Clock

Date: 2014-01-30
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:

Speaker - Rich Ruby, Director of Technology, Avago Technologies, Ltd.
11:05:00-05:00 11:45:00-05:00
2014-01-30

Managing S-parameter Data for 10 to 32 Gb/s Time-Domain Simulations

Date: 2014-01-30
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2014-01-30

Keynote Address: Architecture Revolutions

Date: 2014-01-30
Time: 12:00:00-05:00 - 12:30:00-05:00


Speaker - Thomas Pawlowski, Fellow & Chief Technologist, Micron Technology, Inc.
12:00:00-05:00 12:30:00-05:00
2014-01-30

SI and EMI are Related: Get Used to It

Date: 2014-01-30
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-30

Chip-Package-System ESD Simulation Methodology Using a Chip ESD Compact Model

Date: 2014-01-30
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-30

Cracking the Code of 32 Gbpsec Differential Vias with Advanced Time Domain Methods

Date: 2014-01-30
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-30

Modulation, Equalization, and Forward Error Correction Coding Technologies for a 56 Gbps Chip-to-Module Link

Date: 2014-01-30
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-30

Decoupling Capacitor Optimization by Spectral Current-Based Power Delivery Network Impedance Formulation for SSD/eMMC/uSD Card

Date: 2014-01-30
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2014-01-30

Signal Integrity Analysis of DDR3 High-Speed Memory Interface using HSPICE and Zuken CR-8000 Design Solution

Date: 2014-01-30
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-30

The state of IEEE 802.3bj 100G Backplane Ethernet

Date: 2014-01-30
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-30

Strategies for Determining the Optimal Equalization Partitioning in Multi-Equalizer High Speed Links

Date: 2014-01-30
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-30

RX Jitter, Jitter Measurement, and Relation to Jitter Tolerance and Overall Link Performance

Date: 2014-01-30
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-30

3D Stacked IC Signaling, Jitter and Measurement

Date: 2014-01-30
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-30

Comprehensive Full-Chip Methodology to Verify Electromigration and Dynamic Voltage Drop on High Performance FPGA Designs in the 20nm Technology

Date: 2014-01-30
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2014-01-30

Post-Equalization Metrics at 25 Gbps and Beyond - Panel Discussion

Date: 2014-01-30
Time: 15:45:00-05:00 - 17:00:00-05:00


General Session Files:
15:45:00-05:00 17:00:00-05:00
2014-01-30

Closing the Loop: What Do We Do When Measurements and Simulations Don't Match? - Panel Discussion

Date: 2014-01-30
Time: 15:45:00-05:00 - 17:00:00-05:00


General Session Files:
15:45:00-05:00 17:00:00-05:00
2014-01-30

Optical System Technologies and Integration - Panel Discussion

Date: 2014-01-30
Time: 15:45:00-05:00 - 17:00:00-05:00


General Session Files:
15:45:00-05:00 17:00:00-05:00
2014-01-31

Low Cost Decoupling Solution to Low Power Memory Interface for Tablet Platform

Date: 2014-01-31
Time: 09:00:00-05:00 - 09:40:00-05:00


General Session Files:
09:00:00-05:00 09:40:00-05:00
2014-01-31

Moving Higher Data Rate Serial Links into Production - Issues & Solutions

Date: 2014-01-31
Time: 09:00:00-05:00 - 09:40:00-05:00


General Session Files:
09:00:00-05:00 09:40:00-05:00
2014-01-31

A Novel Scheme to Improve Power Distribution Networks for 20nm FPGA Designs and Beyond

Date: 2014-01-31
Time: 09:50:00-05:00 - 10:30:00-05:00


General Session Files:
09:50:00-05:00 10:30:00-05:00
2014-01-31

How Design of Experiments Saved My CEI VSR 28G Design

Date: 2014-01-31
Time: 09:50:00-05:00 - 10:30:00-05:00


General Session Files:
09:50:00-05:00 10:30:00-05:00
2014-01-31

Higher Speed Ethernet: 40 Gb/s Operation Over Twisted-Pair Copper Cabling

Date: 2014-01-31
Time: 09:50:00-05:00 - 10:30:00-05:00


General Session Files:
09:50:00-05:00 10:30:00-05:00
2014-01-31

Advanced Power-Aware Buffer Behavior Model with Overclocking Solution

Date: 2014-01-31
Time: 10:40:00-05:00 - 11:20:00-05:00


General Session Files:
10:40:00-05:00 11:20:00-05:00
2014-01-31

De-Mystifying the 28 Gb/s SERDES Channel - Design to Measurement

Date: 2014-01-31
Time: 10:40:00-05:00 - 11:20:00-05:00


General Session Files:
10:40:00-05:00 11:20:00-05:00
2014-01-31

Intra-Pair "Unaccounted" Skew - Effects and Suppression

Date: 2014-01-31
Time: 10:40:00-05:00 - 11:20:00-05:00


General Session Files:
10:40:00-05:00 11:20:00-05:00