All-Access Presentations

View all available All-Access Presentations files below:


Date Session Title Start Time End Time
2016-01-19

What Is That Thing Between My Tester and My Socket?

Date: 2016-01-19
Time: 09:00:00-05:00 - 12:00:00-05:00


Speaker - Thomas Bresnan, Sales Account Manager, R&D Altanova
09:00:00-05:00 12:00:00-05:00
2016-01-19

A "Material" World, Modeling Dielectrics and Conductors for Interconnects Operating at 10-50 GBPS

Date: 2016-01-19
Time: 09:00:00-05:00 - 12:00:00-05:00


General Session Files:
09:00:00-05:00 12:00:00-05:00
2016-01-19

A Tutorial on PAM4 Signaling for 56G Serial Link Applications

Date: 2016-01-19
Time: 09:00:00-05:00 - 12:00:00-05:00


General Session Files:
09:00:00-05:00 12:00:00-05:00
2016-01-19

Introduction to Power Integrity *Limited Seating

Date: 2016-01-19
Time: 09:00:00-05:00 - 12:00:00-05:00


General Session Files:
09:00:00-05:00 12:00:00-05:00
2016-01-19

Advanced PI and SI Co-Simulation Skills *Limited Seating

Date: 2016-01-19
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
13:30:00-05:00 16:30:00-05:00
2016-01-19

Understand Silicon Photonics

Date: 2016-01-19
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
- Bowers_Designcon_v5s.pdf (23.75MB)  


Speaker - John Bowers, Professor and Director, Institute of Energy Efficiency, UCSB
13:30:00-05:00 16:30:00-05:00
2016-01-19

Gen4 PCIe Connector & Channel Design and Optimization: 16GT/s for Free

Date: 2016-01-19
Time: 13:30:00-05:00 - 16:30:00-05:00


General Session Files:
13:30:00-05:00 16:30:00-05:00
2016-01-19

My Product Failed EMI - Now What Do I Do?

Date: 2016-01-19
Time: 13:30:00-05:00 - 16:30:00-05:00


Speaker - Kenneth Wyatt, Sr. EMC Engr., Wyatt Technical Services LLC
13:30:00-05:00 16:30:00-05:00
2016-01-19

Reducing Noise in Power Distribution Networks on Time and in Budget

Date: 2016-01-19
Time: 16:45:00-05:00 - 18:00:00-05:00


General Session Files:
16:45:00-05:00 18:00:00-05:00
2016-01-20

Impacts of Dynamic Noise in Multi-Core or SOC Designs

Date: 2016-01-20
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-20

PCB-Substrate Characterization at Multigigahertz Frequencies Through SIW Measurements

Date: 2016-01-20
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-20

A Versatile Spectrum Shaping Scheme for Communicating Beyond Notches in Multi-Drop Interfaces

Date: 2016-01-20
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-20

PAM4 for 400 Gbps: acquisition, measurement, and signal analysis

Date: 2016-01-20
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-20

Novel Methodology of IBIS-AMI hardware Correlation Using Trend and Distribution Analysis for High-Speed SerDes System

Date: 2016-01-20
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-20

25G Long Reach Cable Link System Equalization Optimization

Date: 2016-01-20
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-20

Channel operating margin for 56 Gb/s PAM4 chip-to-chip and backplane interfaces

Date: 2016-01-20
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-20

Evaluation of PDN coupling on SOC

Date: 2016-01-20
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-20

Bluetooth 4.2 and the Internet of Things

Date: 2016-01-20
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:

Speaker - Mark Jakusovszky, US Sales & Marketing Manager, EM Microelectronic-US, Inc.
09:20:00-05:00 10:00:00-05:00
2016-01-20

Tradeoff Between Tightly and Loosely Coupled Differential Vias for Multi-Gbps Design

Date: 2016-01-20
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-20

Analysis, Modeling and Characterization of Multi-Protocol High-Speed Serial Links

Date: 2016-01-20
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:

Speaker - Wendem Beyene, Technical Director, Rambus Inc.
09:20:00-05:00 10:00:00-05:00
2016-01-20

IP-Clean Behavior Modeling and Simulation of High Speed SerDes Receivers

Date: 2016-01-20
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-20

Mueller & Muller CDR Algorithm and Its Application in High Speed Serial Links

Date: 2016-01-20
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-20

Practical Issues and Solutions for Supply Induced Jitter Decomposition in High Speed Serial Links

Date: 2016-01-20
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-20

Enabling HDMI2.0 for Smartphone and Tablet Segments without Active Level Shifter Resulting in Considerable BOM Savings

Date: 2016-01-20
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-20

Electromagnetic Wave Absorption Technology for Stub Effects Mitigation

Date: 2016-01-20
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-20

Design, Modeling and Correlation of Low Swing High Speed Transmitter

Date: 2016-01-20
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-20

100Gbps Dual-Channel PAM4 Transmission Over Datacenter Interconnects

Date: 2016-01-20
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-20

Limitations of the Intra-pair Skew Measurements in Gigabit Range Interconnects

Date: 2016-01-20
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:

Speaker - Yevgeniy Mayevskiy, Principal Engineer, TE Connectivity Medical
11:05:00-05:00 11:45:00-05:00
2016-01-20

A Novel Power-Supply-Induced-Jitter Suppression Technique for High-Speed Interface Using Modulated-PDN

Date: 2016-01-20
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-20

New SI Techniques for Large System Performance Tuning

Date: 2016-01-20
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-20

PAM-4 Simulation to Measurement Validation with Commercially Available Software and Hardware

Date: 2016-01-20
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-20

Challenges and Solutions for Next-Generation OIF CEI-56G-LR and Backplane Interfaces

Date: 2016-01-20
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-20

Significance of Encircled Flux in Metrology of Insertion Loss In Multi-Mode Optical Fiber

Date: 2016-01-20
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-20

Characterizing Geometry-Dependent Crossover Frequency for Stripline Dielectric and Metal Losses

Date: 2016-01-20
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-20

Power Delivery Modeling and Simulation for Server Systems

Date: 2016-01-20
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-20

Jitter, Noise Analysis and BER Synthesis on PAM4 Signals on 400 Gbps Communication Links

Date: 2016-01-20
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-20

100 Gb/s Ethernet: Testing Receiver, Transmitter And Cable Assembly Parameters At Compliance Test Points

Date: 2016-01-20
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-20

Design of a Mobile AP GPU PDN based on Chip Power Model and Measurement

Date: 2016-01-20
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-20

100 Gb/s Serial Transmission Over Copper Using Duo-binary Signaling

Date: 2016-01-20
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-20

Measurement and Simulation of a High-Speed Electro/Optical Channel

Date: 2016-01-20
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-20

IBIS-AMI Based Link Analysis of Realistic 56G PAM4 Channels

Date: 2016-01-20
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-20

Building IBIS-AMI Models from Datasheet Specifications

Date: 2016-01-20
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-20

Low Cost High Speed Internal Cable Solution for Client Systems

Date: 2016-01-20
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:

Speaker - Xiang Li, Staff Analog Engineer, Intel Corp.
14:50:00-05:00 15:30:00-05:00
2016-01-20

ISI Tolerant Signaling: A Comparative Study of PAM4 and ENRZ

Date: 2016-01-20
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-20

Multiport, Asymmetric Fixture Characterization by Custom Calibration Kit

Date: 2016-01-20
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-20

Challenges in IO, Platform Design for a unique PAM3 Interface

Date: 2016-01-20
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-20

BER- and COM-Way Channel Compliance Evaluation: What are the Sources of Difference?

Date: 2016-01-20
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-20

Wireless Charging: Past, Present and Future

Date: 2016-01-20
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-20

Accurate AMI Analysis - Whose Responsibility Is It?

Date: 2016-01-20
Time: 15:45:00-05:00 - 17:00:00-05:00


General Session Files:
15:45:00-05:00 17:00:00-05:00
2016-01-21

Case Study of ESD Issue Debug on Smartphone Reference Design

Date: 2016-01-21
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:

Speaker - Yagnesh Waghela, Mr., Intel technology India PVT LTD
08:30:00-05:00 09:10:00-05:00
2016-01-21

Accurate De-Embedding Using Differential Improved TRL

Date: 2016-01-21
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-21

Comparative Evaluation of 16 GT/s PCIe Gen4 and 22.5 GT/s SAS-4 Standards Evolution and Their Impact on Future Systems and SerDes

Date: 2016-01-21
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-21

In-Depth Analysis of Non-Linear PDN Profile Caused by DDR IO Buffer States

Date: 2016-01-21
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-21

A New Characterization Technique for Glass Weave Skew Sensitivity

Date: 2016-01-21
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-21

Systematic Analysis of Electrical Link Bottlenecks and Strategies for Their Equalization

Date: 2016-01-21
Time: 08:30:00-05:00 - 09:10:00-05:00


General Session Files:
08:30:00-05:00 09:10:00-05:00
2016-01-21

Evaluation of Gallium Nitride MOSFET for VRM Designs

Date: 2016-01-21
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-21

Microwave Interconnect Testing for 12G SDI Applications

Date: 2016-01-21
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-21

Effect of Conductor Profile Structure on Propogation in Transmission Lines

Date: 2016-01-21
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-21

System Level ESD Design and Debug Considerations on Phone and Tablet Products

Date: 2016-01-21
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-21

Are There Any Rules of Thumb When It Comes to 100Gb/S Board Design? A Walkthrough From Physical Domain to Channel Operating Margin (COM) Testing

Date: 2016-01-21
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-21

Analysis and Verification of DDR3/DDR4 Board Channel Impact on Clock Duty-Cycle-Distortion (DCD)

Date: 2016-01-21
Time: 09:20:00-05:00 - 10:00:00-05:00


General Session Files:
09:20:00-05:00 10:00:00-05:00
2016-01-21

A New SI-PI Co-Extraction Methodology & HSPICE Co-Simulation Simplification for A DDR3 Memory Interface

Date: 2016-01-21
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-21

Two for One: Leveraging SerDes Flows for AMI Model Development

Date: 2016-01-21
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
- Two_for_One_v18.pdf (1.30MB)  
10:15:00-05:00 10:55:00-05:00
2016-01-21

Are We Crisp & Clear for DDR4 Memory Channel Radiated Emission?

Date: 2016-01-21
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-21

Optimal DDR4 System with Data Bus Inversion Feature in FPGA High Speed High Bandwidth Memory Interface

Date: 2016-01-21
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-21

A Frequency Domain Approach to Transient Result for Power Distribution Network Analysis

Date: 2016-01-21
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-21

Novel PI Flow Driven Using Powertree for Easier Data Visualization and Automation

Date: 2016-01-21
Time: 10:15:00-05:00 - 10:55:00-05:00


General Session Files:
10:15:00-05:00 10:55:00-05:00
2016-01-21

Specification Development for a High Speed Clock Forwarded Interface: DPHY2.0

Date: 2016-01-21
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-21

PDN Prototyping and Optimization at an Early Design Stage

Date: 2016-01-21
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-21

56 Gbps PCB Design Strategies for Clean, Low-Skew Channels

Date: 2016-01-21
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-21

Block-Level Modeling Based Power and Signal Integrity Performance Optimization of Integrated Core and Memory System

Date: 2016-01-21
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-21

Signal and Power Integrity PCB Characterization for Multi GHz High Speed Interface

Date: 2016-01-21
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-21

Chip and Package-Level Wideband EMI Analysis for Mobile DRAM Devices

Date: 2016-01-21
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-21

Design and Analysis of Silicone Rubber-based TERAPOSER for LPDDR4 Memory Test

Date: 2016-01-21
Time: 11:05:00-05:00 - 11:45:00-05:00


General Session Files:
11:05:00-05:00 11:45:00-05:00
2016-01-21

Optimized placement of microwave absorbers on high speed digital channels with SI and EMI considerations

Date: 2016-01-21
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-21

Power Integrity Design, Analysis, and Verification for Large Printed Circuit Boards

Date: 2016-01-21
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-21

The History and Evolution of IBIS Modeling

Date: 2016-01-21
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:

Speaker - Michael Mirmak, Data Center Platform Applications Engineer, Intel Corp.
14:00:00-05:00 14:40:00-05:00
2016-01-21

Lower Loss and Process Friendly Multi-layer Flexible Interconnect

Date: 2016-01-21
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-21

Electrical and Thermal Consequences of Non-Flat Impedance Profiles

Date: 2016-01-21
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-21

Chip, Package, and PCB Co-Design Methodology to Address PDN Design Challenges for High-Performance Socs and FPGAs

Date: 2016-01-21
Time: 14:00:00-05:00 - 14:40:00-05:00


General Session Files:
14:00:00-05:00 14:40:00-05:00
2016-01-21

Clock Recovery for Signals with Spread Spectrum Clock Through Lossy Channels

Date: 2016-01-21
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:

Speaker - Kan Tan, Principle Engineer, Tektronix
14:50:00-05:00 15:30:00-05:00
2016-01-21

'What-If' Jitter Analysis from Synthesized Realistic PD Noise

Date: 2016-01-21
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-21

Mid-Frequency Noise Coupling Between DC-DC Converters and High-Speed Signals

Date: 2016-01-21
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-21

Old School RF Structure Meets Modern Signal Integrity: The Beatty Standard

Date: 2016-01-21
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-21

Platform & SDRAM Power Integrity Design Optimization and Methodology for LPDDR4 and Beyond

Date: 2016-01-21
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:
14:50:00-05:00 15:30:00-05:00
2016-01-21

Improved Formulas for Crosstalk Coefficients

Date: 2016-01-21
Time: 14:50:00-05:00 - 15:30:00-05:00


General Session Files:

Speaker - Eric Bracken, Senior R&D Fellow, Ansys Inc.
14:50:00-05:00 15:30:00-05:00
2016-01-21

Getting Smooth Copper and Keeping It

Date: 2016-01-21
Time: 15:45:00-05:00 - 17:00:00-05:00


General Session Files:
15:45:00-05:00 17:00:00-05:00
2016-01-21

Target Impedance and Rogue Waves

Date: 2016-01-21
Time: 15:45:00-05:00 - 17:00:00-05:00


General Session Files:
15:45:00-05:00 17:00:00-05:00